Job: Verification Engineer for Functional Verification

Job: Verification Engineer for Functional Verification
We are looking for new Verification Engineers for our Design Center in Novi Sad, Serbia

Job description

Involvement in all verification stages for complex SoC
Testbench generation using Verilog, SystemVerilog or SystemC with OVM / UVM
Development of Verification Plan and associated testcases
Setup of simulation environment for regression
RTL coding using VHDL or Verilog

Qualification

Minimum […]

Job: Verification Engineer for Functional Verification

Job: Verification Engineer for Functional Verification
Werden Sie Consultant für unserer Niederlassung in München

Stellenbeschreibung

RTL coding using VHDL or Verilog
Testbench generation using Verilog, SystemVerilog or SystemC
Development of Verification Plan and associated testcases
Setup of simulation environment for regression
Gate-level simulation

Qualifikation

Minimum Bachelors degree in Electronics resp. Dipl.-lng. (FH, TU) Nachrichtentechnik, Elektrotechnik or equivalent specialization
2 – 5 years experience in […]