Job: Verification Engineer for Functional Verification

We are looking for new Verification Engineers for our Design Center in Novi Sad, Serbia

Job description

  • Involvement in all verification stages for complex SoC
  • Testbench generation using Verilog, SystemVerilog or SystemC with OVM / UVM
  • Development of Verification Plan and associated testcases
  • Setup of simulation environment for regression
  • RTL coding using VHDL or Verilog


  • Minimum Bachelors degree in Electronics or equivalent specialization
  • 2 – 5 years experience in digital design based on VHDL and/or Verilog HDL in a UNIX workstation environment
  • Good knowledge of Verification methodologies and tools (Cadence, Mentor, Synopsys)
  • Knowledge of Specman-e and eRM is a plus
  • Knowledge of scripting languages (Perl, Tcl, Python, etc.) is a plus
  • Gate-level simulation experience is a plus
  • Excellent communication and interpersonal skills need to include the ability to conduct business with English language.