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18 01, 2017

Job: Verification Engineer for Functional Verification

  • Wednesday, 18. January, 2017

Job: Verification Engineer for Functional Verification
We are looking for new Verification Engineers for our Design Center in Novi Sad, Serbia

Job description

Involvement in all verification stages for complex SoC
Testbench generation using Verilog, SystemVerilog or SystemC […]

24 01, 2014

Job: Verification Engineer for Functional Verification

  • Friday, 24. January, 2014

Job: Verification Engineer for Functional Verification
As Consultant for our office in Munich

RTL coding using VHDL or Verilog
Testbench generation using Verilog, SystemVerilog or SystemC
Development of Verification Plan and associated testcases
Setup of simulation environment for regression
Gate-level […]