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24 01, 2014

Job: Verification Engineer for Functional Verification

  • Friday, 24. January, 2014

Job: Verification Engineer for Functional Verification
As Consultant for our office in Munich

RTL coding using VHDL or Verilog
Testbench generation using Verilog, SystemVerilog or SystemC
Development of Verification Plan and associated testcases
Setup of simulation environment for regression
Gate-level […]