Job: Verification Engineer for Functional Verification
As Consultant for our office in Munich

RTL coding using VHDL or Verilog
Testbench generation using Verilog, SystemVerilog or SystemC
Development of Verification Plan and associated testcases
Setup of simulation environment for regression
Gate-level simulation

Qualification

Minimum Bachelors degree in Electronics resp. Dipl.-lng. (FH, TU) Nachrichtentechnik, Elektrotechnik or equivalent specialization
2 – 5 years experience in digital […]