Job: Verification Engineer for Functional Verification
As Consultant for our office in Munich
- RTL coding using VHDL or Verilog
- Testbench generation using Verilog, SystemVerilog or SystemC
- Development of Verification Plan and associated testcases
- Setup of simulation environment for regression
- Gate-level simulation
- Minimum Bachelors degree in Electronics resp. Dipl.-lng. (FH, TU) Nachrichtentechnik, Elektrotechnik or equivalent specialization
- 2 – 5 years experience in digital design and debug based on VHDL and/or Verilog HDL in a UNIX workstation environment
- Good knowledge of Verification methodologies and tools (Cadence, Mentor)
- We are looking for engineers with 2-5 years active relevant design or field engineering experience.
- Excellent communication and interpersonal skills need to include the ability to conduct business with English language.
- The position requires readiness to travel.